Superconducting rapid single-flux-quantum (RSFQ) logic is a promising technology for future high-performance computing with its exceptional ultrafast switching speed and ultralow switching energy. However, designing RSFQ circuits is challenging due to the need for precise timing alignment, especially in the placement and routing process. We present a physical design framework for RSFQ circuits that includes a clock-aware length-matching placer and a multi-terminal router. The placer optimizes clock distribution and timing by heuristically assigning clock pulses and reformulating placement as a shortest path problem. It uses dynamic programming to reduce vertical wire length and applies a barycenter-like method for iterative improvement. The router handles splitter-aware routing with a two-layer Manhattan model, combining track assignment, cycle resolution, and a hierarchical splitter-tree method with max-flow detour insertion. Additionally, we propose a length-matching placement method for multiphase clocking RSFQ circuits. This method introduces two new RSFQ cells to simplify clock networks in two-phase designs. It uses a column-wise max-flow method for clock distribution and dynamic programming to minimize wire length while maintaining fixed orders. A novel length-aware reordering technique further improves optimization. Experimental results on benchmarks show that our methods outperform existing approaches.