The scalability of superconducting quantum computers at cryogenic temperatures is severely hindered by the substantial number of wires connecting the dilution refrigerator to room temperature. A promising solution involves operating room-temperature CMOS control circuits directly in the cryogenic environment (Cryo-CMOS) to reduce these interconnections. Critical to efficient large-scale Cryo-CMOS circuit design, however, is the availability of accurate transistor models simulating CMOS characteristics at ultra-low temperatures. This presentation will review the primary modeling approaches for Cryo-CMOS transistors: 1) the industry-standard BSIM model; 2) recent machine learning-based modeling techniques; and 3) methods grounded in cryogenic device physics. We will evaluate the advantages and limitations of each approach and conclude with a discussion on future research directions.