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Design and Evaluation of Single Flux Quantum Circuits with Josephson Inductors Fabricated by Low Critical Current Density Process

Chikai Nakamura (Yokohama National University) ; Nobuyuki Yoshikawa (Yokohama National University) ; Yuki Yamanashi (Yokohama National University)

For the large-scale integration of superconducting quantum computers, a promising approach is to use control circuits located on the same temperature stage as the many qubits inside a dilution refrigerator.
Since dilution refrigerators have limited cooling power, the control circuits must operate with extremely low power consumption. Single Flux Quantum (SFQ) circuits are well-suited for this purpose, as they can operate at high speed and low power under cryogenic conditions, making them ideal for use as control circuits for superconducting qubits in ultra-low-temperature environments.
The bit energy of an SFQ circuit is given by IcΦ0 [J], where IC is the critical current of the Josephson junction (JJ) and Φ0 is the magnetic flux quantum. To minimize power consumption, it is desirable to use a low critical current density (JC) process, which enables the design of low-power circuits with reduced IC. However, to maintain circuit functionality, the product LIC must remain constant in SFQ circuits. Therefore, simply reducing IC leads to an increase in L, requiring longer superconducting interconnects and resulting in larger circuit area. In this study, we reduced circuit area by replacing superconducting wiring with Josephson inductors (JI). Circuit fabrication was carried out using the four-layer niobium low-JC process (JC =1 kA/cm2) developed by the National Institute of Advanced Industrial Science and Technology (AIST).
We designed and simulated five types of circuits using JI. Compared to conventional circuits, layout area was reduced by an average of 55%. The bias margin was also comparable to that of conventional designs. Moreover, we found that the delay variation due to IC fluctuations was suppressed to 1/2 to 1/3 by using JIs.

Acknowledgement

This work was
supported by JSPS KAKENHI Grant Number JP22H01542.

Poster

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Architecture

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October 27, 13:30 → 15:00

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