Stochastic computing (SC) is a type of approximate computation that uses the probability of “1” in a binary sequence as a numerical representation called a stochastic number (SN). While it can perform multiplication and addition using a small number of logic gates, it has the disadvantage of requiring time for information representation. To address this issue, we are considering applying SC to a single-flux quantum circuit with excellent high-speed performance. In this study, we propose a circuit that performs integer division on the input SN, referred to as a stochastic integer division circuit. While division in SC has the drawback of requiring large-scale circuits, the proposed circuit achieves division using a simple circuit by limiting it to integer division.
The proposed circuit uses a clock divider to reduce the frequency of the input SN by a factor of 1/n, and then uses frequency synchronization in the superconducting random number generator to replicate the reduced SN and output an SN that is uncorrelated with the input and equal to 1/n of the input signal. We performed simulations on the proposed integer division circuit that divides the input SN by 3 and confirmed the input and output waveforms. We assume the High-speed Standard Process of the National Institute of Advanced Industrial Science and Technology in simulations, with an operating frequency of 30 GHz. With an input SN bit length of 4096 bits, an output SN of 0.202 was obtained when the input SN was 0.602. It can be confirmed that an SN of approximately 1/3 was obtained.