State-of-the-art superconducting qubits are usually based on Al/AlOx/Al Josephson Junctions (JJ) and fabricated using a CMOS foundry incompatible process, relying on double angle shadow evaporation and lift-off techniques [1]. IMEC has recently demonstrated a high-yield, high-coherence superconducting qubit overlap process on 300mm wafers in its CMOS pilot line [2,3]. This work focuses on improving device variability, by reducing JJ resistance variability, and improving process reproducibility and qubit coherence by careful optimization of the individual processing steps. More specifically, the shape of the bottom and top electrodes of the JJ and their related defectivities are carefully controlled by optimizing the dry etching, wet clean and Ar milling recipes. The AlOx barrier is also investigated by adapting the Ar milling and oxidation processes. These results are supported by morphological analysis and room-temperature electrical characterization. One notable example is the implementation of temperature variation during Al electrode dry etching on the electrostatic chuck [4] which improved critical dimension (CD) uniformity across the wafer and enabled control over the tapering angle of the electrode sidewalls. In parallel, alternative fabrication approaches are explored to continue improving device performances, paving the way for the fabrication of well-controlled, reproducible, high-yield and long-coherence time qubit circuits in an industrial processing environment.