Superconducting integrated circuits offer high speed and low energy consumption advantage but face inherent limits in scalability due to routing congestion, long interconnect delays, and low integration scale. Meanwhile, for single flux quantum (SFQ) superconducting circuit, physical separation between clock and data paths would help timing control for high frequency operation. Implementing multi-logic-layer three-dimensional (3D) stacking has emerged as a promising approach to address these challenges. We first developed the double-Josephson-junction-layer process, termed Nb08, introducing unshunted Josephson junction transmission lines (JTLs) with inductive biasing in the upper layer to realize theoretically zero static-power interconnect transmission. Using Nb08, we successfully designed and cryogenically verified a half-adder, confirming the viability of the low-power interconnect approach. Based on this, we further developed SIMIT Nb08b, a double-logic-layer process in which logic gates can occupy both layers and clock distribution could be physically isolated in the upper layer. The half-adder by SIMIT Nb08b achieves a 33% further area reduction compared with SIMIT Nb08, while sustaining a wider bias-current operating margin. Compare with the SIMIT Nb03b single-layer process, it delivers a 68% area reduction, 53.7% fewer number of Josephson junctions, and a 63.8% lower power dissipation. The double-logic-layer methodology offers enhanced routing flexibility, scalable high-frequency timing control, and strong potential for multi–clock-domain systems, deeply pipelined architectures, and high-density SFQ logic, laying a robust fabrication–design co-optimization foundation for next-generation high-performance, energy-efficient superconducting processors.