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Quantum computer system architecture for fault-tolerant computation

Teruo Tanimoto (Kyushu University)

To make practical use of quantum computing in real-world applications, it is essential to achieve low logical error rates using Quantum Error Correction Codes (QECCs). However, QECCs have low encoding efficiency, requiring a large number of physical qubits, which makes the realization of fault-tolerant quantum computers challenging. Additionally, because various layers of technology, such as quantum devices and QECCs, are advancing simultaneously, it becomes difficult to keep up with the progress of quantum computer systems that combine these technologies. To address these challenges, efforts are needed to abstract quantum computing systems and effectively reduce the required resources. In my presentation, I will introduce recent initiatives related to these points.

Acknowledgement

N/A

Invited

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Architecture

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October 29, 11:55 → 12:20

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