Superconducting Rapid Single Flux Quantum (RSFQ) circuits are gaining attention as a promising circuit technology for high-speed and low-power computing systems. RSFQ circuits utilize pulse logic, which expresses logical values using voltage pulses. The property of using voltage pulses allows direct realization of Stochastic Computing (SC), which is also being researched in CMOS logic circuits.
In this study, we propose an SC division circuit for RSFQ circuits. The proposed circuit performs division between fixed-point numbers with values less than 1. Data feedback is required to realize division circuits, and maintaining data consistency in the feedback part is challenging in RSFQ circuits, where each gate operates as a pipeline stage. We propose a SC division circuit optimized for RSFQ circuits based on a SC division method proposed for CMOS circuits with a small feedback loop [1].
In the original circuit, two parallel magnitude comparators are used to generate two correlated bit streams, which are then passed through a multiplexer to perform division. The only feedback is the path that returns the output of the multiplexer to its input. The proposed circuit generates bit streams similar to the original with cyclic registers formed by connecting DFFs instead of large magnitude comparators. The circuit uses a confluence buffer for the multiplexer. It reduces the feedback path to one gate stage.
The error of the proposed circuit was evaluated by simulation. When the input bit width was 4 bits and the number of cycles for one operation was 16, the mean absolute error was 0.061, which was smaller than 1/16.