The integration of cryogenic digital control and readout close to the qubits chips in the same cryostat has the potential to solve the major roadblocks in scaling quantum computers to the complexity levels necessary for practical applications. This would avoid the challenges of generating qubit control and readout signals at room-temperature and transmitting them with minimum distortions, crosstalk, and noise to qubits over long coaxial cables. In addition, having this massive cabling with the associated cryogenic connector, filter, and attenuator overhead leads to major reliability and heat load problems which alone might prevent the scaling.
SEEQC implemented the qubit control, including 1Q and 2Q gates, and readout functions using energy-efficient SFQ digital circuits. While the insertion of the SFQ chips co-integrated with qubit chips eliminated many problems listed above, the fidelity and speed of the digitally controlled quantum gates are lagging below the performance of conventional microwave techniques. The performance improvement will come with further sophistication of SFQ circuits while minimizing their power dissipation. In addition, one needs to address specific to superconducting circuits problems such as flux trapping, poor scaling of operational margins, fabrication yield, and lack of dense memories. Possible ways to address these challenges will be discussed.